Design of Processing Element (PE3) for Implementing Pipeline FFT Processor

A Pipeline Fft Processor

In this paper, we discuss the design and implementation of a high-speed, low power 1024-point pipeline FFT processor. Key features are flexible internal data length and a novel processing element. The FFT processor, which is implemented in a standard 035 pm CMOS process, is efficient in term of power consumption and chip area.

Design of an Effective Pipeline FFT/IFFT Processor

This investigation proposes the novel radix-4 and radix-4 algorithms with the low computational complexities of the radix-16 and radix-64 algorithms and the low hardware requirement of the radix-4 algorithm. Base on the multiplierless radix-4 butterfly structure, the proposed radix-4 single-path delay feedback (R4SDF) design and radix-4 single-path delay feedback (R4SDF) design support the 4096...

Design and Implementation of a 1024-point Pipeline FFT Processor

Design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the r a d i ~ 2 ~ algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in PLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT proce...

A New Approach to Pipeline FFT Processor

A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide and conquer approach. Radix-22 algorithm has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. The single-path delay-feedback architecture...

Design of Fft Processor